FIG. 1 is a block diagram of a prior-art read channel 100 for a hard drive. Read channel 100 receives an analog input signal 121 corresponding to data stored on the hard drive and generates a digital decoded output signal 129 representing the data stored on the hard drive.
In particular, analog-to-digital converter (ADC) 122 digitizes analog input signal 121 to generate digital input signal 123. Digital finite impulse response (DFIR) filter equalizer 124 equalizes digital input signal 123 to generate equalized digital signal 125. Soft detector 126 converts equalized digital signal 125 into soft values, such as multi-bit log likelihood ratio (LLR) values 127, where each LLR value has a hard-decision sign bit and a multi-bit (e.g., 4-bit) confidence value. Soft detector 126 implements a suitable detection technique, such as Viterbi soft-output detection or maximum a posteriori (MAP) detection, to generate LLR values 127. Decoder 128 decodes the LLR values to generate decoded output signal 129. For example, if the data stored on the hard drive is encoded using a low-density parity check (LDPC) code, then decoder 128 performs LDPC decoding to generate decoded output signal 129 from LLR values 127.
Phase detector 130 processes equalized digital signal 125 from equalizer 124 and the sign bits of LLR values 127 from soft detector 126 to generate an estimated timing error signal 131. In one conventional implementation, phase detector 130 generates estimated timing error signal 131 by (i) convolving the sign bits with a finite impulse response (FIR) filter, (ii) generating the difference between the FIR filter output and a one-cycle-delayed version of equalized digital signal 125, and (iii) multiplying that difference by an estimate of the slope of equalized digital signal 125. Loop filter 132 integrates estimated timing error signal 131 to output an averaged error signal 133. Time-base generator (e.g., local oscillator (LO)) 134 generates LO clock signal 135. Interpolator 136 shifts the phase of LO clock signal 135 based on averaged error signal 133 to generate sampling clock signal 137, which determines the timing of the sampling of analog input signal 121 by ADC 122.
In hard-drive read-channel technology, the signal-to-noise ratio (SNR) continues to decrease due to increasing storage density of the disks. Conventional timing-recovery phase detectors that estimate timing information from equalized samples (such as equalized digital signal 125) and hard decisions (such as the sign bits of LLR values 127) might not operate properly in low-SNR environments, resulting in an unacceptably high loss-of-lock rate (LOLR), which reduces system throughput.